1. Field of the Disclosure
Generally, the present disclosure relates to the field of integrated circuits and, more particularly, to integrated circuits including nonvolatile memory devices.
2. Description of the Related Art
Nonvolatile memory, such as, for example, flash memory, may be used in various storage devices, such as, for example, secure digital memory cards (SD cards), USB sticks, solid-state drives (SSDs), and internal memory of various electronic devices, such as, for example, mobile phones, tablet computers, media players, etc. Further applications of nonvolatile memory include embedded systems, wherein nonvolatile memory blocks including nonvolatile memory are provided in addition to logic devices, and wherein the nonvolatile memory devices and the logic devices are physically and electrically integrated on a single substrate. Devices that may be provided on the substrate in addition to the nonvolatile memory cells may include field effect transistors and other circuit elements, such as capacitors, inductivities, diodes and/or resistors. Embedded systems including nonvolatile memory find applications in various fields, such as, for example, in automotive, industry and communication market segments. Integrating nonvolatile memory and logic circuitry on a single substrate can help to improve performance and reduce costs compared to solutions wherein nonvolatile memory and logic circuitry are provided on separate substrates, for example, due to an elimination of input/output buffers, design flexibility, lower power consumption and/or system-on-a-chip capability.
Examples of known nonvolatile memory cells include those described in U.S. Pat. Nos. 6,747,310 and 7,868,375. Nonvolatile memory cells as described in U.S. Pat. Nos. 6,747,310 and 7,868,375 include a source region and a drain region that are formed in a bulk semiconductor substrate. Between the source region and the drain region, a channel region is provided that is doped differently than the source region and the drain region. Over the channel region, a floating gate and a select gate are provided. Over the floating gate, a control gate is provided, and an erase gate is provided over the source region. The select gate, the floating gate, the control gate structure and the erase gate are electrically insulated from each other and from the source, drain and channel regions by electrically insulating materials. The floating gate may be surrounded by electrically insulating material so that it is electrically floating. The source region, the drain region, the select gate, the control gate and the erase gate may have respective electrical contacts connected thereto so that voltages can be applied to the source region, the drain region and the select, control and erase gates for performing operations of programming, erasing and reading the nonvolatile memory cell.
Issues associated with nonvolatile memory cells as described above include a relatively complex processing of the semiconductor structure for the formation of the nonvolatile memory cells, wherein a relatively large number of additional process steps and masks formed by means of photolithography are required, in addition to those employed for the formation of logic transistors. When nonvolatile memory cells are provided on a same semiconductor structure as logic transistors formed in accordance with a relatively advanced technology, for example, in accordance with the 28-nm technology node or below, the additional process steps and the additional photolithography steps performed for the formation of the additional masks may adversely affect the device behavior of the logic transistors. Furthermore, it may be difficult to form silicon germanium in P-channel logic transistors for improving the mobility of holes in the channel thereof when the logic transistors are formed on the same substrate as nonvolatile memory devices because processing steps performed for the formation of the silicon germanium can adversely affect the nonvolatile memory cells.
Other types of nonvolatile memory cells that can be formed on a same substrate as logic transistors include nonvolatile memory cells that have a charge trapping layer instead of a floating gate electrode for storing an electrical charge that is representative of a bit of data written to the nonvolatile memory cell. In some examples of nonvolatile memory cells having a charge trapping layer, a split gate structure may be provided. Charge trapping nonvolatile memory cells having a split gate structure may be formed in a front-end-of-line module of a semiconductor manufacturing process, wherein, however, issues similar to those described above in the context of nonvolatile memory cells including a floating gate may occur.
The present disclosure provides semiconductor structures including nonvolatile memory cells and methods for the formation thereof that may help to substantially overcome or at least reduce some or all of the above-mentioned issues.